clock page 1 of 3 raltron electronics corp. 10651 n.w. 19 th st miami, florida 33172 u.s.a. phone: (305) 593-6033 fax: (305) 594-3973 e-mail: sales@raltron.com web: http://www.raltron.com cld/cldp series: clock oscillator, lvds, +3.3 vdc or +2.5vdc description: a crystal controlled, high frequency, highly stable oscillator, adhering to low voltage differential signaling (lvds) standards. the output can be tri-stated to facilitate testing or combined multiple clocks. the device is contained in a sub-miniature, very low profile, leadless ceramic smd package with 6 gold contact pads. this miniature oscillator is ideal for today's automated assembly environments. applications and features: infiniband; 10gbe; network processors; soho routing; switches; wan interfaces common frequencies: 106.25 mhz; 125 mhz; 150 mhz; 155.52 mhz; 156.25 mhz; 161.1328 mhz +3.3 vdc or +2.5vdc lvds frequency range from 50.000 to 315 mhz no multiplication miniature ceramic smd package available on tape and reel lead free and rohs compliant absolute maximum ratings: parameter symbol value unit operating temperature range ta -40?+85 c storage temperature range t(stg) -55?+90 c supply voltage vcc -0.5?+5.0 vdc maximum input voltage vi vss-0.5?vcc+0.5 vdc maximum output voltage vo vss-0.5?vcc+0.5 vdc electrical parameters: parameter symbo l test conditions *1 value unit nominal frequency fo 50.000 ~ 315.00** mhz supply voltage vcc +3.3 or +2.5 5% vdc supply current is 80.0 max ma output logic type lvds load connected between out and complementary out 100 ? voh output logic high 1.43 typ, 1.6 max vdc vol output logic low 0.9 min, 1.10 typ vdc vod differential output 247 min, 330 typ, 454 max mv differential output error 50 max mv vos offset voltage 1.125 min, 1.25 typ, 1.375 max vdc output levels os offset error 50 max mv duty cycle dc measured at 50% of vcc 40/60 to 60/40 or 45/55 to 55/45 % rise / fall time tr / tf measured at 20/80% and 80/20% vcc levels 0.6 typ *2 ns integrated phase tji rms, fj = 12 khz?20 mhz 0.3 typ** ps integrated phase rms tii offset frequency 50khz to 80mhz 0.5 typ** ps deterministic period jitter tdj using wavecrest analyz. 0.0typ ** ps random period jitter trj using wavecrest analyz. 2.5 typ ** ps jitter j peak to peak jitter tp-p using wavecrest analyz. 25 typ** ps phase noise typ. @155.52mhz ( ? f) ( ? f) ( ? f) ( ? f) ? f= 10 hz ? f= 1 khz ? f= 10 khz ? f 100 khz -65 -120 -140 -145 dbc/hz dbc/hz dbc/hz dbc/hz overall frequency stability ? f/fc op. temp., aging, load, supply and cal. variations 20, 25, 50, or 100 max *3 ppm pin 1 output enabled output disabled en dis high voltage or no connect ground 0.7 ? vcc min 0.3 ? vcc max vdc vdc *1 test conditions unless stated otherwise: nominal vcc, nominal load, +25 3 c *2 frequency dependent *3 not all stabilities available with all temperature ranges?please consult factory for availability
clock page 2 of 3 raltron electronics corp. 10651 n.w. 19 th st miami, florida 33172 u.s.a. phone: (305) 593-6033 fax: (305) 594-3973 e-mail: sales@raltron.com web: http://www.raltron.com 123 4 5 6 . 1 9 7 . 0 0 8 .276 .008 7.0 0.2 5 . 0 0 . 2 indicates pin 1. .079 max. 2.00 max. .200 .100 5.08 2.54 . 1 5 0 3 . 8 1 .055 1.40 typ. . 0 5 0 1 . 2 7 .079 typ. 2.00 typ. .100 2.54 .071 1.80 solder pattern 2.20 .087 part numbering system: series symmetry temperature range (c) frequency stability (overall) frequency (mhz) cld: +3.3vdc clock with lvds comp. output cldp: +2.5vdc clock with lvds comp. output a: 40/60 to 60/40% t: 45/55 to 55/45% r: 0?+50 s: 0?+70 u: -20?+70 v: -40?+85** k: 20 ppm** i: 25 ppm** h: 50 ppm j: 100 ppm 50.000?315.000 example: cldash-155.520 clock oscillator, 7x5mm package, +3.3 vdc supply voltage, lvds output, standard symmetry, 0?+70 c operating temperature range, 50 ppm total frequency stability, 155.520 mhz **above 300mhz extended temp range and 25ppm stability may not be available, jitter may vary upon spec requirements. please consult the factory for any custom requirements. mechanical parameters: outline tolerance: 0.006? / 0.15mm (unless otherwise specified) pin functions: [1] enable/ disable [2] no connect [3] case ground [4] output [5] comp. output [6] supply voltage marking: cldash 155.52 ral d/c *0.01 f external by-pass filter is recommended as seen on solder pattern.
clock page 3 of 3 raltron electronics corp. 10651 n.w. 19 th st miami, florida 33172 u.s.a. phone: (305) 593-6033 fax: (305) 594-3973 e-mail: sales@raltron.com web: http://www.raltron.com reflow profile: **rohs compliant**
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